Master of Science Thesis Defense by: Richard J. Muri
When: Monday,
December 10, 2018
2:00 PM
-
4:00 PM
Where: Science & Engineering Building, Lester W. Cory Conference Room: Room 213A
Cost: Free
Description: Topic: Processor-In-Memory Computer Architectures
Location: Lester W. Cory Conference Room, Science & Engineering Building (SENG), Room 213A
Abstract:
A processor-in-memory (PIM) computer architecture is any design that performs some subset of logical operations in the same location as memory. The traditional model of computing involves a processor loading data from memory to perform operations, with a bus connecting the processor and memory. While this technique works well in many situations, a growing gap between memory performance and processor performance has led some researchers to develop alternative architectures.
This thesis includes a discussion of what is a PIM architecture, as well as motivations, applications, and limitations of PIM. After providing background information on the subject, a Field Programmable Gate Array (FPGA) implementation of a PIM enhanced microcontroller is presented. Using an Artix-7 FPGA, an ATmega103 microcontroller soft core is modified to include a PIM core as an accelerator. The sample application of AES encryption provides a comparison between the baseline processor and the PIM enhanced machine.
NOTE: All ECE Graduate Students are ENCOURAGED to attend.
All interested parties are invited to attend. Open to the public.
Advisor: Paul J. Fortier
Committee Members: Dr. David P. Rancour, Department of Electrical & Computer Engineering; and
Dr. Gaurav Khanna, Physics Department
*For further information, please contact Dr. Paul J. Fortier at 508.999.8544, or via email at pfortier@umassd.edu.
Location: Lester W. Cory Conference Room, Science & Engineering Building (SENG), Room 213A
Abstract:
A processor-in-memory (PIM) computer architecture is any design that performs some subset of logical operations in the same location as memory. The traditional model of computing involves a processor loading data from memory to perform operations, with a bus connecting the processor and memory. While this technique works well in many situations, a growing gap between memory performance and processor performance has led some researchers to develop alternative architectures.
This thesis includes a discussion of what is a PIM architecture, as well as motivations, applications, and limitations of PIM. After providing background information on the subject, a Field Programmable Gate Array (FPGA) implementation of a PIM enhanced microcontroller is presented. Using an Artix-7 FPGA, an ATmega103 microcontroller soft core is modified to include a PIM core as an accelerator. The sample application of AES encryption provides a comparison between the baseline processor and the PIM enhanced machine.
NOTE: All ECE Graduate Students are ENCOURAGED to attend.
All interested parties are invited to attend. Open to the public.
Advisor: Paul J. Fortier
Committee Members: Dr. David P. Rancour, Department of Electrical & Computer Engineering; and
Dr. Gaurav Khanna, Physics Department
*For further information, please contact Dr. Paul J. Fortier at 508.999.8544, or via email at pfortier@umassd.edu.
Contact:
ECE: Electrical & Computer Engineering Department 508.999.9164 http://www.umassd.edu/engineering/ece/
Topical Areas: General Public, University Community, College of Engineering