MASTER OF SCIENCE THESIS DEFENSE BY: Sri Shanmukha Naraharisetti
When: Wednesday,
December 9, 2015
12:30 PM
-
2:30 PM
Where: Science & Engineering Building, Lester W. Cory Conference Room: Room 213A
Cost: Free
Description: TOPIC: SQUARE ROOT CARRY SELECT ADDER USING BEC FOR AREA EFFICIENT PROCESSORS
LOCATION: Lester W. Cory Conference Room, Science & Engineering Building (Group II), Room 213A
ABSTRACT:
Arithmetic functions are the basic operations in many data processors. In most of the digital adders the speed of addition is limited by time taken for the carry to propagate through the adder. Square Root Carry Select Adder (SQRT CSLA) is one of the adders which is used to perform the addition operations very fast [1], but due to the ripple carry adders (RCA) used in the SQRT CSLA module the number of AOI gates used here are more compared to the AOI gates used in the modified SQRT CSLA which leads them to occupy more area. Modified SQRT CSLA limits the number of gates (area) by using Binary to Excess 1 Converters (BEC) in place of RCAs.
The Area, power and Delay parameters of the modified SQRT CSLA using BEC are determined from simulations with Synopsys tools and compared with SQRT CSLA which uses RCA. Based on the comparison of results of the ordinary module and modified module, the better Design of the two models is brought out.
NOTE: All ECE Graduate Students are ENCOURAGED to attend.
All interested parties are invited to attend. Open to the public.
Advisor: Dr. David P. Rancour
Committee Members: Dr. Lance Fiondella, Department of Electrical & Computer Engineering and Dr. Gaurav Khanna, Physics Department
*For further information, please contact Dr. David Rancour at 508.999.8466, or via email at drancour@umassd.edu.
LOCATION: Lester W. Cory Conference Room, Science & Engineering Building (Group II), Room 213A
ABSTRACT:
Arithmetic functions are the basic operations in many data processors. In most of the digital adders the speed of addition is limited by time taken for the carry to propagate through the adder. Square Root Carry Select Adder (SQRT CSLA) is one of the adders which is used to perform the addition operations very fast [1], but due to the ripple carry adders (RCA) used in the SQRT CSLA module the number of AOI gates used here are more compared to the AOI gates used in the modified SQRT CSLA which leads them to occupy more area. Modified SQRT CSLA limits the number of gates (area) by using Binary to Excess 1 Converters (BEC) in place of RCAs.
The Area, power and Delay parameters of the modified SQRT CSLA using BEC are determined from simulations with Synopsys tools and compared with SQRT CSLA which uses RCA. Based on the comparison of results of the ordinary module and modified module, the better Design of the two models is brought out.
NOTE: All ECE Graduate Students are ENCOURAGED to attend.
All interested parties are invited to attend. Open to the public.
Advisor: Dr. David P. Rancour
Committee Members: Dr. Lance Fiondella, Department of Electrical & Computer Engineering and Dr. Gaurav Khanna, Physics Department
*For further information, please contact Dr. David Rancour at 508.999.8466, or via email at drancour@umassd.edu.
Contact:
ECE: Electrical & Computer Engineering Department 508.999.9164 http://www.umassd.edu/engineering/ece/
Topical Areas: General Public, University Community, Electrical and Computer Engineering