MASTER OF SCIENCE THESIS DEFENSE BY: Md Alimul Risvey
When: Tuesday,
August 30, 2016
10:00 AM
-
12:00 PM
Where: Science & Engineering Building, Lester W. Cory Conference Room: Room 213A
Cost: Free
Description: TOPIC: DESIGN OF 10-NM FINFET
LOCATION: Lester W. Cory Conference Room, Science & Engineering Building (Group II), Room 213A
ABSTRACT:
The FinFET is a 3D field effect transistor which is the new driving force of the semiconductor industry that provides superior scalability with minimum short channel effects. In this work Synopsys Sentaurus TCAD tools were used to design FinFETs of 10 nm channel length. FinFET design parameters like fin height, thickness were selected based on the standard design rules described by the scholarly articles on FinFETs. Other design parameters like source/drain doping, channel doping were selected based on performance. Bulk and SOI FinFETs were designed and characteristics were studied. Necessary performance parameters of FinFETs such as threshold voltage, maximum transconductance, on-off-currents, subthreshold slope, Drain Induced Barrier Lowering (DIBL) were extracted for both the designs.
NOTE: All ECE Graduate Students are ENCOURAGED to attend.
All interested parties are invited to attend. Open to the public.
Advisor: Dr. David P. Rancour
Committee Members: Dr. Dayalan P. Kasilingam, Department of Electrical & Computer Engineering and Dr. Gaurav Khanna, Physics Department
*For further information, please contact Dr. David P. Rancour at 508.999.8466, or via email at drancour@umassd.edu.
LOCATION: Lester W. Cory Conference Room, Science & Engineering Building (Group II), Room 213A
ABSTRACT:
The FinFET is a 3D field effect transistor which is the new driving force of the semiconductor industry that provides superior scalability with minimum short channel effects. In this work Synopsys Sentaurus TCAD tools were used to design FinFETs of 10 nm channel length. FinFET design parameters like fin height, thickness were selected based on the standard design rules described by the scholarly articles on FinFETs. Other design parameters like source/drain doping, channel doping were selected based on performance. Bulk and SOI FinFETs were designed and characteristics were studied. Necessary performance parameters of FinFETs such as threshold voltage, maximum transconductance, on-off-currents, subthreshold slope, Drain Induced Barrier Lowering (DIBL) were extracted for both the designs.
NOTE: All ECE Graduate Students are ENCOURAGED to attend.
All interested parties are invited to attend. Open to the public.
Advisor: Dr. David P. Rancour
Committee Members: Dr. Dayalan P. Kasilingam, Department of Electrical & Computer Engineering and Dr. Gaurav Khanna, Physics Department
*For further information, please contact Dr. David P. Rancour at 508.999.8466, or via email at drancour@umassd.edu.
Contact:
ECE: Electrical & Computer Engineering Department 508.999.9164 http://www.umassd.edu/engineering/ece/
Topical Areas: General Public, University Community, College of Engineering, Electrical and Computer Engineering