University Events

Description: Topic: Design and Optimization of Interconnection and Memory Subsystems for Future Manycore Computing

Location: College of Engineering Conference Room, Textiles Building (TXT), Room 101E

Abstract:
With ever-increasing core count, worsening dark silicon constraints, and growing performance demand of modern data-centric applications (e.g., big data and internet-of-things (IoT) applications), energy- efficient and low-latency data communications on and off the chip are becoming essential for emerging manycore computing systems. But unfortunately, due to their poor scalability, the state-of-the-art electrical interconnects and DRAM based main memories are projected to exacerbate the latency and energy costs of data communications. Recent advances in silicon photonics, 3D stacking, and non-volatile memory technologies have enabled the use of cutting-edge interconnection and memory subsystems, such as photonic interconnects, 3D-stacked DRAM, and phase change memory. These innovations have the potential to enhance the performance and energy-efficiency of future manycore systems. However, these emerging interconnection and memory subsystems still face many technology-specific challenges along with process, environment, and workload variabilities, which negatively impact their reliability overheads and implementation feasibility. My research has contributed several solutions that overcome multitude of these challenges and improve the energy-efficiency and reliability of manycore systems integrating photonic interconnects and emerging memory (3D-stacked DRAM and phase change memory) subsystems.

In this talk, I will give an overview of my research contributions. Particularly, I will discuss about two of my research contributions in detail. First, I will discuss a novel low-overhead technique for runtime management of laser power in photonic networks-on-chip architectures. This technique makes use of semiconductor on-chip optical amplifiers to achieve loss-aware savings in laser power. Second, I will talk about my invented 3D decomposed DRAM architecture called 3D-ProWiz. 3D-ProWiz architecture employs through-silicon vias (TSVs) at subarray-level granularity to eliminate the need of using global wires, which in turn significantly reduces the latency and energy costs of DRAM accesses. Last, I will briefly discuss about my short- and long-term research and teaching goals, along with my collaboration and funding plans.

Biography:
Ishan Thakkar has a BE in electronics and communication engineering from the L.D. College of Engineering of Gujarat University, Gujarat, India. He received his MS degree in electrical engineering from Colorado State University (CSU), Fort Collins, CO, USA, where he is currently finishing his PhD in electrical engineering. His current research interests include silicon photonics, photonic networks-on-chip, high-speed optical interfaces, DRAM architectures, and non-volatile memories. He is the recipient of the best paper award from IEEE/ACM SLIP 2016 workshop, a best paper nomination from the IEEE ISQED 2016 conference, and a best paper nomination from the TMSCS journal in 2017 for his research contributions. Ishan has served as an Organizing Committee Member of the 2017 IEEE International Green and Sustainable Computing (IGSC) conference. He has also been involved in the Technical Program Committee of the 2017 IEEE International Green and Sustainable Computing (IGSC) conference and the 2018 IEEE Embedded and VLSI Design conference.

The seminar is open to the public free of charge.

*For further information, please contact Dr. Karen L. Payton at 508.999.8434, or by via email at kpayton@umassd.edu.